As semiconductor devices become more complex and include more and more components, it becomes necessary to develop new structures and fabrication techniques which minimize the overall size of the device. One such technique for reducing the physical size of the device is to form multi-layered structures where metal interconnects overlay one another and are separated from each other by interlevel dielectric layers. The overlying metal interconnects are electrically coupled with each other and with conductive structures on the substrate surface through via holes and contact openings in the interlevel dielectric layers. As the size of the device is reduced, the contact and via holes must necessarily be made smaller and placed closer together; but, the thickness of the interlevel dielectric material must continue to be sufficient to electrically isolate the overlying metal interconnects. The competing requirements for a small via diameter and a thick isolation layer increases aspect ratio (depth/diameter) of the via holes.
The small diameter of the vias and the relatively thick interlevel dielectric layer makes the formation of a highly reliable contact structure difficult. Not only must a small opening be formed in a thick dielectric material, but also, a low electrical contact resistance must be achieved. In addition, the number and complexity of the processing steps must be held to a minimum to keep manufacturing costs low. A particular problem develops where, for example, electrically resistive materials form over an underlying metal layer to which a contact opening has been formed. To avoid excessive contact resistance, the electrically resistive material must be removed prior filling the via with another metal layer. The resistive material is often removed by an insitu cleaning process immediately prior to deposition of the overlying metal layer. Typically, the resistive material is sputtered away or reactively etched using energetic atoms and ions. So long as the size of the via opening is large, the resistive surface layers on the metal are removed, leaving a clean metal surface. However, in the case of a via having a high aspect ratio, material being removed from the surface of the metal impacts the sidewall of the via dislodging insulative material from the sidewall. Once dislodged from the sidewall, the insulative material falls to the exposed metal surface and reforms a resistive layer. Thus, the insitu cleaning process is defeated by a self-generated mechanism.
From another perspective, high-aspect ratio vias are also difficult to form because of their small diameter and the need to place them in precise locations. The via opening must be formed over a predetermined contact site on an a structure underlying the insulating layer. If the via opening is misaligned to the contact site, when the via is filled an ohmic contact may not be formed because the misalignment causes a reduction in electrically conductive surface area in the contact. This is because a portion of the metal filling the via contacts insulating material instead of the conductive material at the contact site. If the via opening is completely misaligned an open is created in the circuit causing complete device failure.
As the trend toward fabrication of devices having smaller feature sizes and higher performance continues, better materials and processes must be used to avoid processing problems such as that describe above. The careful selection of proper materials can achieve both better device performance, and minimize production costs by reducing the need for special processing steps.